The present invention generally relates to a SRAM cell that has a compact size achieved by eliminating two pull-up transistors and a method for fabricating the cell and more particularly, relates to a compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors and a method for fabricating the compact SRAM cell.
High-density SRAM devices are desirable for high-speed cache applications. As the technology of process and device integration is advanced, more and more systems are being incorporated in a single chip. The system-on-chip (SOC) approach has become a trend for future electronic systems to meet both cost and performance requirements.
Traditionally, a SRAM cell is formed by six transistors, i.e. two pull-up pMOS devices, two pull-down nMOS devices and two others for NMOS transfer devices. Since data stored in the SRAM cells are latched by a pair of back-to-back invertors, no refresh operation and thus no associated circuitry are necessary. Furthermore, SRAM is inherently faster than DRAM (access time of 0.8 ns vs. 12 ns for DRAM) due to the fact that no write-back, precharge and refresh operations are required. In order for SRAM to be economically employed in electronic systems for high-performance, continuous efforts are being made to reduce its cost and chip size. In the past, thin film transistors were implemented to form high-density SRAM. The thin film transistors are used for the pull-up devices and are formed on top of the other devices such that the area may be saved. However, this approach not only leads to an increase in the process steps, but also results in relatively poor performance due to the limitation of TFT device performance.
More recently, four transistor SRAM transistors have been proposed and its development has gained a significant attention in the semiconductor industry. For instance, a four-T (transistor) single-port SRAM cell has been reported by NEC, titled xe2x80x9cA 2.9 xcexcm2 Embedded SRAM Cell With Co-Salicide Direct-Strap Technology for 0.18 xcexcm High Performance CMOS Logic, IEDM 97, p 847,1997. This single-port SRAM cell shares the transfer gates with the pull-up devices and therefore eliminates two devices per cell. This approach has significantly reduced the cell size, and is a very attractive design for a high-density integration. Since the pull-up and the transfer devices in NEC""s cell are pMOS devices, for the unselected wordlines, the wordline voltage and all the bitline voltages are held high. The nodes are isolated since the pMOS devices are turned off. However, the leakage charge from the internal high node is constantly replenished by the off-state current flowing through the pMOS pull-up devices. There are two drawbacks with this design, (1) the cell size is not minimal, since there is a minimal ground rule specified between p-well and n-well for placing mixed pMOS and nMOS devices in a cell, and (2) read/write disturb on the non-selected cell is an issue, since their bitlines are not constantly held high when the array is active.
It is therefore an object of the present invention to provide a SRAM cell that does not have the drawbacks or shortcomings of the conventional SRAM cells.
It is another object of the present invention to provide a SRAM cell that incorporates a vertical NMOS transfer device, a pair of pull-down nMOS devices and a pair of vertical high resistive elements.
It is a further object of the present invention to provide a compact SRAM cell that incorporates high-resistive refactory metal-silicon-nitrogen resistive elements in place of pull-up pMOS transistors.
It is another further object of the present invention to provide a compact SRAM cell wherein the cell size can be only 2.5xc3x97 to 3xc3x97 to that of DRAM cells.
It is still another object of the present invention to provide a compact SRAM cell that incorporates TaSiN resistive elements in place of pull-up pMOS transistors.
It is yet another object of the present invention to provide a method for forming a compact SRAM cell with refractory metal-silicon-nitrogen resistive elements in place of its pull-up transistors.
In accordance with the present invention, a compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements as its pull-up transistors and a method for fabricating the compact SRAM cell are provided.
In a preferred embodiment, a compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up resistive lead elements are provided which include a semi-conducting substrate; a pair of NMOS transfer devices formed vertically on the substrate; a bitline contacting an n+ region in the substrate in-between two adjacent transfer devices; a pair of pull-down nMOS devices where sources are connected to ground and drains are connected to a pair of vertical high resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd.
In the compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements as its pull-up elements, the refractory metal-silicon-nitrogen is formed of a refractory metal that is selected from the group consisting of Ta, Nb, V, W or Ti. The semi-conducting substrate may be a silicon-on-insulator substrate, for example, a silicon layer of about 300 nm thick formed on top of a buried oxide layer of about 100 nm thick. The cell may further include a shallow trench isolation formed in-between active areas on the semi-conducting substrate. The refractory metal-silicon-nitrogen may be TaSiN or may be TaSiN that consists of between about 10 at. % and about 55 at. % Ta, between about 10 at. % and about 45 at. % Si and between about 30 at. % and about 80 at. % N. The pair of vertical high resistive elements may be formed in the shape of studs. The pair of pull-down nMOS devices may further include gates formed of doped polysilicon.
The present invention is further directed to a method for forming a compact SRAM cell with refractory metal-silicon-nitrogen resistive elements as its pull-up elements which can be carried out by the operating steps of providing a semi-conducting substrate that has a silicon top layer; forming a first opening for vertical transfer gates; depositing a gate oxide layer and a gate conductor layer sequentially on top of the substrate; after patterning the pull-down nMOS gates, anisotropically etching the gate conductor layer to form gates for pull-down transistors and a pair of sidewall spacers in the first opening for vertical transfer gates; ion implanting into the silicon top layer forming n+ source/drain regions for the pull-down transistors, and the vertical transfer gates; forming insulating sidewall spacers on the gates for pull-down transistors and an insulating layer on the sidewall in the opening of the vertical transfer gates; depositing an oxide insulating layer on top of the substrate and planarizing a top surface; etching a second plurality of openings in the oxide insulating layer for contact studs for the pull-down transistors and for the vertical transfer gate; filling the second plurality of openings with a conductive metal and planarizing top surfaces of the contact studs formed; etching a third plurality of openings in the oxide insulating layer defining regions for the resistive elements; sputter depositing refractory metal-silicon-nitrogen into the third plurality of openings forming the resistive elements; annealing the resistive elements at a temperature below a melting temperature of the refractory metal-silicon-nitrogen and planarizing top surfaces of the resistive elements; forming metal interconnects on top of the contact studs and the resistive elements; and forming a metal conductor on top of the contact stud to the junctions of vertical transfer gates serving as bitline.
The method for forming a compact SRAM cell with refractory metal-silicon-nitrogen resistive elements as its pull-up elements may further include the step of providing the semi-conducting substrate in a silicon-on-insulator substrate, or the step of providing the semi-conducting substrate in a silicon-on-insulator substrate consisting of about 300 nm thick silicon layer on about 100 nm thick oxide layer. The method may further include the step of forming the first opening to form vertical transfer gates to a depth of about 150 nm, or the step of depositing the gate conductor layer in doped polysilicon. The method may further include the step of forming the insulating sidewall spacers on the gates from an oxide layer, and forming the insulating layer on the sidewall spacers in the opening for vertical transfer gate from silicon nitride. The method may further include the step of depositing the oxide insulating layer to a thickness of at least 3000 xc3x85, or the step of depositing the oxide insulating layer of a material selected from the group consisting of PSG, BPSG, CVD TEOS and CVD oxide.
The method may further include the step of planarizing the oxide insulating layer by a chemical mechanical polishing technique, or the step of filling the second plurality of openings by a CVD tungsten technique. The method may further include the step of sputter depositing TaSiN into the third plurality of openings forming the resistive elements, or the step of sputter depositing TaSiN consisting of between about 10 at. % and about 55 at. % Ta, between about 10 at. % and about 45 at. % Si and between about 30 at. % and about 80 at. % N. The method may further include the step of depositing the refractory metal-silicon-nitrogen wherein the refractory metal is selected from the group consisting of Ta, Nb, V, W and Ti. The method may further include the step of forming metal interconnects for ground on top of the contact studs, and forming metal interconnects for Vdd on top of the resistive elements.